It is often needed to keep a MOS (Metal-Oxide-Semiconductor) transistor switched-off in the case of a lack of power supply of the electronic device incorporating the MOS transistor and in the case where the drain terminal of the MOS transistor undergoes an abrupt change of voltage. In fact, in this case, the voltage change of the drain terminal is transferred to the gate terminal, due to the parasitic capacitance between the drain and the gate terminals. This variation of the voltage of the gate terminal can switch on the MOS transistor and, especially in case the MOS transistor is used as a switch for an external load in high-power applications, it can damage the MOS transistor.
Referring to FIG. 1A, a known approach for keeping a MOS transistor M switched-off following abrupt changes of the voltage of drain terminal D is to use a pull-down resistor Rpd (more in general, a pull-down circuit) connected to the gate terminal G of the MOS transistor M. The pull-down resistor Rpd has the function of quickly discharging (for example towards the source S connected to ground) the voltage of the gate terminal G, thereby reducing the effects due to the capacitive coupling between the drain terminal D and the gate terminal G.
It is further needed to perform the test of the gate oxide of the MOS transistor (used for example in high-power applications), to detect defects that may be present at the end of the manufacturing process of the MOS transistor on the silicon wafer, before the phase of wire bonding and of packaging.
Referring to FIG. 1A, a known technique for performing the test of the gate oxide of the MOS transistor M is that referred to as the “gate stress test”, which involves three steps. In the first step, the gate terminal G of the MOS transistor M is placed under a high-impedance condition, on the gate terminal G of the MOS transistor M it is forced a value of the test voltage Vsp within the typical operational range (via a pad GST connected to the gate terminal G), thus on the pad GST it is measured a first value of the current IL1 which flows in the gate terminal G. In the second step, on the gate terminal G a value of the test voltage Vsp outside the typical operational range is forced. In the third step, the gate terminal G of the MOS transistor M is placed again under the high-impedance condition, on the gate terminal G of the MOS transistor M the value of test voltage Vsp within the typical operational range is forced (via the pad GST), thus on the pad GST it is measured a second value of current IL2 which flows in the gate terminal G. If the difference between the second value of current IL2 and the first value of current IL1 is negligible, the test of the oxide of the gate G of the MOS transistor M is successful, i.e. the MOS transistor M is considered defect-free; in the opposite case, the MOS transistor M is considered defective.
For further details related to the test of the gate oxide, see for example the following documents: V. Malandruccolo, M. Ciappa, W. Fichtner, “Novel solution for the built-in gate oxide stress of LDMOS in integrated circuits for automotive applications”, European Test Sumposium IEEE 2009, pp. 67-72; V. Malandruccolo, M. Ciappa, H. Rothleitner, W. Fichtner, “New on-chip screening of gate oxides in smart power devices for automotive applications”, IEEE 2009, pp. 573-578.
Therefore it is necessary to use a circuit which is capable of keeping the MOS transistor switched-off in case of lack of power supply and in case of an abrupt change in the voltage of the drain terminal, and which is, at the same time, capable of performing the test of the gate oxide.
Referring to FIG. 1A, a known technique is to use the pull-down resistor Rpd connected between the gate terminal G of the MOS transistor M and ground. In case the supply voltage of the circuit 1 is not present and in case the gate terminal G has a change in the voltage due to a change of the voltage of the drain terminal D, the pull-down resistor Rpd has the function to switch-off the MOS transistor M by discharging towards ground the generated current which flows from the gate terminal G towards ground across the pull-down resistor Rpd. Moreover, a test pad GST connected to the gate terminal G is used, to perform the test of the gate oxide of the MOS transistor M.
It has been observed that a drawback of this typical approach is that it is not optimized, because it requires a trade-off value of the resistance of the pull-down resistor Rpd. In fact, the test of the gate oxide requires a high value of the resistance to limit the current sink during the test, while switching-off the MOS transistor requires a small value of the resistance to allow the voltage of the gate terminal to be discharged quickly towards ground.
A further known technique for performing the test of the gate oxide of the MOS transistor and for keeping the MOS transistor switched-off is that shown in FIG. 1B. The electronic circuit 50 comprises a pull-down resistor Rpd, the n-type MOS transistor M′, a pnp-type bipolar transistor T and a Zener diode DZ, which are connected as shown in FIG. 1B.
The switch-off of the MOS transistor M′ is achieved via the transistor T. In fact, in case of lack of power supply and in case of an abrupt change of the voltage of the drain terminal D′ of the MOS transistor M′, the transistor T enters into conduction and prevents the gate terminal G′ of the MOS transistor M′ from reaching voltage values greater than the voltage difference VEB between the emitter E and the base B of the transistor T (for example, VEB=0.7 V).
Therefore the MOS transistor M′ is switched-off, provided that the threshold voltage Vth of the MOS transistor M′ is greater than the voltage difference VEB. This condition is fulfilled for MOS transistors having a thick gate oxide (i.e. with a oxide thickness greater than 120 Angstrom), but it is not fulfilled for MOS transistors having a thin gate oxide, which are widely used in power devices in the BCD6 technology. Hence, the circuit 50 has the drawback that it is not capable of passively switching-off a MOS with a threshold voltage Vth smaller than the voltage difference VEB, such as for example MOS transistors having a thin gate oxide (oxide thickness smaller than 120 Angstrom).